Printing processes have been used for patterning of lines or patterns in electronic or semiconductor devices. Gravure offset printing was used to make 50-μm-wide conductor lines on ceramic substrates and to pattern thin-film transistors for low-cost displays. Offset printing was used for the fabrication of capacitors and printed and plated metal lines as narrow as 25 μm. Printed circuit boards and integrated circuit packaging are popular applications of screen printing in the electronics industry. Inkjet printing has also become popular in various industrial fabrication processes, from microelectronics soldering, micro-machined parts, to multicolor polymer light-emitting diode displays.
However, currently it is problematic to directly print metal or polymeric conductor ink onto hydrophobic surfaces, because the commercially available conductive inks tend to be hydrophilic and de-wet into separate droplets. Cracking of the conductor lines is prevalent on dielectric polymers such as poly(vinylidene fluoride/trifluoroethylene, or P(VDF-TrFE), and leads to failure of the thin film transistor (TFT) array
FIG. 8 illustrates a prior art thin-film transistor (TFT) circuit 800 with two-layer dielectric to avoid the problem of printing directly on hydrophobic P(VDF-TrFE). The TFT 800 includes a substrate 810, a 2-layer dielectric 820, a semiconductor layer 830; and source, drain, and gate electrodes 832, 834, and 836. The 2-layer dielectric 820 includes a ferroelectric PVDF-TrFE layer 822 (800 nm) and another thin layer of dielectric 825 polymer PVP (100 nm) that is hydrophilic and compatible for printing. FIG. 9 illustrates prior art curves for the two-layer dielectric TFT shown in FIG. 8. The curves 910, 920, and 930 show the source-drain current Isd as function of the gate voltage Vg. The curves 910, 920, and 930 correspond to different values of the source-drain voltages. The curves 910, 920, and 930 may correspond to values of the source-drain voltages of −5V, −10V, and −40V, respectively. The values of the Isd I0, I1, I2, I3, I4, I5, and I6 may be 0, −1×10−7 A, −2×10−7 A, −3×10−7 A, −4×10−7 A, −5×10−7 A, and −6×10−7 A, respectively. The values of the Vg V−2, V−1, V0, V1, and V2 may be −50 V, −25 V, 0 V, 25 V, and 50 V, respectively. As the gate voltage varies the source-drain current shows no or little hysteresis behavior. Accordingly, the prior art design does not allow data storage as a non-volatile memory cell.